The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device having a dual work function gate.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. In FET devices with a channel having a relatively short length, the FET can experience a number of undesirable electrical characteristics referred to as short channel effects (SCE). SCE generally occur when the gate does not have adequate control over the channel region, and can include threshold voltage (Vt) roll-off, off current (loff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions decrease, SCE can become more severe. SCE is the result of intrinsic properties of the crystalline materials used in the FET devices. Namely, the band gap and built-in potential at the source/body and drain/body junctions are non-scalable with the reduction of physical device dimensions, such as a reduction in channel length.
A typical technique used to minimize SCE is to fabricate FETs with extensions as part of the source/drain areas. The extensions are commonly formed using a lightly doped drain (LDD) technique as is well known in the art.
However, there still exists a need in the art for semiconductor devices, such as MOSFETs, that have reduced SCE and for fabrication techniques to make those semiconductor devices.
According to one aspect of the invention, a MOSFET is provided. The MOSFET includes a source and a drain formed in a layer of semiconductor material and a gate disposed above the layer of semiconductor material to define a channel interposed between the source and the drain. The gate includes a center gate electrode portion having a first work function and being spaced from the layer of semiconductor material by a center gate dielectric, the center gate dielectric establishing a first capacitance from the center gate electrode portion to the layer of semiconductor material; and a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion and each lateral gate electrode portion having a second work function different from the first work function, and each lateral gate electrode portion being spaced from the layer of semiconductor material by a lateral gate dielectric portion, each lateral gate dielectric portion establishing a second capacitance from the lateral gate electrode portions to the layer of semiconductor material, the second capacitance different from the first capacitance, and the first work function, the second work function, the first capacitance and the second capacitance cooperate so that an absolute value of a device threshold in a center region of the channel is lower than an absolute value of a device threshold in regions of the channel adjacent each of the source and the drain.
According to another aspect of the invention, a method of fabricating a MOSFET having a dual work function gate is disclosed. The method includes providing a layer of semiconductor material; forming a pair of spaced apart lateral gate dielectric portions on the layer of semiconductor material; forming a center gate dielectric portion on the layer of semiconductor material between the lateral gate dielectric portions; forming a center gate electrode portion on the center gate dielectric portion, the center gate electrode portion having a first work function; and forming a lateral gate electrode portion adjacent each sidewall of the center gate electrode portions and on respective lateral gate dielectric portions, the lateral gate electrode portion having a second work function different from the first work function.